1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a process for forming a bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing.
2. Description of the Related Art
Photolithography is a semiconductor fabrication process that is widely used. for patterning material layers on a semiconductor wafer or structure. The material layers can be non-metal (e.g. silicon, polysilicon), metal (e.g. aluminum), etc.
A layer of photoresist is formed over the material layer to be patterned, and exposed to light through a mask which has opaque and transparent areas corresponding to the desired pattern. Light passing through the transparent areas in the mask causes a chemical reaction in the underlying areas of the photoresist such that these areas will be dissolved away when the wafer is exposed to a developing solution.
The result is a photoresist layer having openings therethrough which correspond to the transparent areas of the mask. The patterned photoresist layer is then used as an etch mask such that areas of the material layer which are exposed by the openings in the photoresist layer will be selectively removed upon exposure to an appropriate etching solution. This is possible by selecting the etching solution to have a much higher etch rate for the material layer than for the photoresist. Preferably the etch rate for the photoresist will be substantially zero.
With feature sizes of integrated circuits constantly shrinking, photolithographic resolution or definition is becoming increasingly sensitive to reflection during the light exposure step. This is especially problematic at very short wavelengths in the ultraviolet band, including deep ultraviolet exposure which is conventionally performed at a wavelength of 248 nanometers.
As illustrated in FIG. 1, a semiconductor structure 10 which is in an intermediate step in a fabrication process includes a material layer 12 which is to be patterned by photolithography, and a photoresist layer 14 which is formed on the material layer 12. The material layer 12 can be polysilicon which is being patterned into a field effect transistor gate or interconnect, or any other applicable material. The layer 12 is formed on a silicon or other semiconductor substrate which is not shown.
A ray of light is illustrated as entering the photoresist layer 14 at an off-normal angle as indicated at 16, and passing through the layer 14 as indicated at 18. The ray is reflected from the surface of the layer 12 back into the layer 14 as indicated at 20. The reflected ray 20 enlarges the exposed area of the photoresist layer 14 to include an area that was not intended to be exposed, resulting in a larger area being removed during development than was desired.
This phenomenon in general degrades the resolution or definition capability of the photolithographic process. Although FIG. 1 illustrates only unwanted reflection caused by-off-normal incident light, light can also be reflected off underlying device features to produce similar results.
In order to inhibit reflection of light back into a photoresist layer, Bottom Anti-Reflective Coatings (BARC) have been developed as illustrated in FIG. 2, in which similar elements are designated by the same reference numerals used in FIG. 1. As viewed in the figure, an anti-reflective coating 22 is provided between the material layer 12 and the photoresist layer 14
A ray of light is incident on and passes through the photoresist layer 14 as indicated at 16,18, and a portion of this light is reflected back into the photoresist layer 14 as indicated at 20. Another portion, of this light passes through the anti-reflective coating 22 as indicated at 24, is reflected from the surface of the layer 12, and passes back through the layer 22 into the layer 14 as indicated at 26.
The index of refraction n, extinction coefficient k, and thickness t of the anti-reflective coating 22 are selected such that the light 26 will be 180° or ½ wavelength out of phase with the light 20. Destructive interference will occur between the light 20,26 in the photoresist layer 14 causing the light 20,26 to mutually cancel. In this manner, reflection of light from the surface of the material layer 12 into the photoresist layer 14 is effectively inhibited.
An anti-reflective layer or coating 22 which is effective for deep ultraviolet lithography is described in U.S. patent application Ser. No. 08/479,718, entitled “SILICON OXIME FILM”, filed Jun. 7, 1995, by D. Foote, and is incorporated herein by reference in its entirety. This coating is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) over the material layer to be patterned as described above.
The material of the coating is called silicon oxime, and has the generic chemical formulation SiNO:H, being a compound of silicon, oxygen, nitrogen, and residual hydrogen in varying proportions which are selected in accordance with a particular application. The index of refraction n, extinction coefficient k, and thickness t of the layer are selected to provide half-wavelength cancellation of light reflected into an overlying photoresist layer 14 as described above.
FIG. 3 illustrates the desired appearance of the structure 10 after a portion of the photoresist layer 14 has been exposed and developed to form an opening 14′. The layer 14 acts as an etch mask for subsequent processing such that the portions of the layer 22 and layer 12 underlying the opening 14′ can be selectively removed by etching using a substance that will not significantly affect the photoresist layer 14. The walls of the opening 14 are substantially vertical as desired.
FIG. 4 is similar to FIG. 3, but illustrates “footing” which is caused by chemical interaction between the anti-reflective layer 22 and the photoresist layer 14. The footing appears as horizontally enlarged portions 22′ which extend from the lower edges of the photoresist layer 14 into the opening 14′. The footing is undesirable because it degrades the resolution or definition of the photolithographic process.
Where the anti-reflective layer 22 is formed of silicon oxime as described above, the footing is caused by chemical interaction between amines (hydrogen-nitrogen bonds) in the silicon oxime layer 22 and the material of the photoresist layer. This is facilitated by the fact that silicon oxime is a base, whereas the photoresist material is an acid.
It is known that this interaction, and thereby the footing, can be inhibited by forming a silicon dioxide barrier layer on the surface of the silicon oxime layer before forming the photoresist thereon. The barrier layer acts as a seal or cap which separates the amines in the silicon oxime layer from the photoresist layer 14.
Prior art methods include forming a silicon dioxide barrier layer on a silicon oxynitride (SiON:H) layer, which is another substance used as an antireflection coating. This method includes deposition in the reactor used to form the silicon oxynitride layer itself. Such deposition is limited by conventional techniques to forming a silicon dioxide layer having a thickness in excess of 100 angstroms. A silicon dioxide layer of such thickness is difficult to remove if required in the processing environment to which the present invention relates.
Another method includes growing a silicon dioxide layer on a silicon oxime layer in a downstream plasma system using oxygen gas. This method is limited in that it is only capable of forming a silicon dioxide layer which is too thin (less than 10 angstroms) to eliminate footing.
FIG. 6 illustrates a detrimental situation which can result from removing a thick (100 angstroms or more) silicon dioxide barrier layer from a field-effect transistor structure. An exemplary semiconductor structure 30 includes a silicon substrate 32. A thin gate oxide layer 34 is formed on the substrate 32, and a polysilicon gate 36 is formed on the gate oxide. The gate 36 was photolithographically patterned, and had a silicon oxime layer, a 100+ angstrom silicon dioxide layer, and a photoresist layer formed thereon which were removed after the patterning was completed.
The silicon dioxide barrier layer was removed using a suitable etchant. In this configuration, the lateral edges of the gate oxide layer 34 were also exposed to the etchant. During the length of time required to remove the silicon dioxide layer, exposed edge portions of the layer 34 were also removed by the etchant to produce significant undercutting as indicated at 34′. This adversely affects the gate width of the transistor and the control over the underlying channel by a voltage applied to the gate 36.
As described in the above referenced U.S. Pat. No. 5,710,067, the escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. The increasing demands for high densification impose correspondingly high demands on photolithographic techniques.
Conventional photolithographic techniques employed during various phases in the manufacture of semiconductor devices involve the formation of an anti-reflective coating (ARC), also characterized as an anti-reflective layer (ARL), typically positioned between a semiconductor substrate and a photoresist material. ARCs are conventionally made of various materials, including organic and inorganic. For example, inorganic materials conventionally employed for ARCs include silicon nitride, silicon oxynitride, α-carbon, titanium nitride, silicon carbide and amorphous silicon. Organic materials conventionally employed for ARCs include spin-on polyimides and polysulfones. Conventional ARCs are designed, by appropriate adjustment of variables such as composition, deposition conditions and reaction conditions, to exhibit the requisite optical parameters to suppress multiple interference effects caused by the interference of light rays propagating in the same direction due to multiple reflections in the photoresist film. The effective use of an ARC enables patterning and alignment without disturbance caused by such multiple interference, thereby improving line width accuracy and alignment, critical factors with respect to achieving fine line conductive patterns with minimal interwiring spacing. The use of an ARC is particularly significant when forming a via or contact hole over a stepped area, as when etching a dielectric layer deposited on a gate electrode and gate oxide formed on a semiconductor substrate in manufacturing a field effect transistor.
The physics involved in ARCs is known and the use of ARCs is conventional and, hence, will not be set forth herein detail. See, for example, T. Tanaka et al., “A New Photolithography Technique with Antireflective Coating on Resist: ARCOR,” J. Electrochem. Soc., Vol. 137, No. 12, December 1990, pp. 3900-3905. ARCs have improved the accuracy of ultra-violet and deep ultra-violet lithography, and expanded to the use of ion beam, I-line, KrF and ArF excimer laser lithography. T. Ogawa et al., “SiOxNy:H, high performance anti-reflective layer for current and future optical lithography.” Recently, an effort has been made to develop improved dry etching techniques for ARCs, including particularly silicon oxynitride. M. Armacost et al., “Selective Oxide: Nitride Dry Etching in a High Density Plasma Reactor,” Electrochemical Society Meeting, 1993, Extended Abstract, column 93-1, p. 369. Efforts have been made to engineer the optical parameters of an ARC, as by adjusting process variables impacting the refractive index during plasma enhanced chemical vapor deposition (PECVD). T. Gocho et al., “Chemical Vapor Deposition of Anti-Reflective Layer Film for Excimer Laser Lithography,” Japanese Journal of Applied Physics, Vol. 33, January.1994, Pt. 1, No. 1B, pp. 486-490.
Notwithstanding such efforts, conventional photolithographic capabilities constitute a severe limiting factor in reducing the design rule or maximum dimension of a conductive pattern and, hence, increasing densification.
Accordingly, there exists a need for materials having the requisite optical properties for use in ARCs which enable accurate control of the width of conductive lines of conductive patterns and minimizing the interwiring spacing therebetween, particularly for materials which exhibit desirable etch characteristics.